Modeling and optimizing the power performance of large matrices multiplication on multi-core and GPU platform with CUDA

Authors:
Da Qi Ren;Reiji Suda
Affiliations:
Department of Computer Science, University of Tokyo, Tokyo, Japan and JST, CREST, Japan;Department of Computer Science, University of Tokyo, Tokyo, Japan and JST, CREST, Japan
Venue:
PPAM'09 Proceedings of the 8th international conference on Parallel processing and applied mathematics: Part I
Year:
2009

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Abstract

The power efficiency of large-scale computing on multiprocessing systems is an important issue that interrelated to both of the hardware architectures and the software methodologies. Aiming to design power-efficient high performance program, we have measured the power consumption of large matrices multiplication on multi-core and GPU platform. Based on the obtained power characteristic values of each computing component, we abstract the energy estimations by incorporating physical power constrains from the hardware devices and analysis of the program execution behaviors. We optimize the matrices multiplication algorithm in order to improve its power performance, and the efficiency promotion has been finally validated by measuring the program execution.