Modified model for settling behavior of operational amplifiers in nanoscale CMOS

Authors:
Hamidreza Rezaee-Dehsorkh;Nassim Ravanshad;Reza Lotfi;Khalil Mafinezhad
Affiliations:
Integrated Systems Laboratory, Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran;Integrated Systems Laboratory, Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran;Integrated Systems Laboratory, Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran;Integrated Systems Laboratory, Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

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Abstract

An accurate time-domain model for the settling behavior of folded-cascode operational amplifiers is presented. Using a velocity-saturation model for MOS transistors makes the proposed model suitable for nanoscale CMOS technologies. Both linear and nonlinear settling regimes and their combination are considered. Transistor-level HSPICE simulation results of a fully differential single-stage folded-cascode amplifier using BSIM4v3 models of a standard 90-nm CMOS process are presented to verify the accuracy of the proposed models.