Design issues in low-voltage high-speed current-mode logic buffers

Authors:
Payam Heydari
Affiliations:
University of California, Irvine, CA
Venue:
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Year:
2003

Citing 2
Cited 1

Digital integrated circuits: a design perspective

Digital integrated circuits: a design perspective
Design of Analog CMOS Integrated Circuits

Design of Analog CMOS Integrated Circuits

A 10-Gb/s CML I/O circuit for backplane interconnection in 0.18-µm CMOS technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The circuit design issues in regard to the CML buffer are compared with those in a conventional CMOS inverter. It is shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.