Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V
IEEE Transactions on Circuits and Systems II: Express Briefs
A low-power low-offset dynamic comparator for analog to digital converters
Microelectronics Journal
A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process
Analog Integrated Circuits and Signal Processing
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A 0.5 V high-speed comparator with rail-to-rail input range is presented. Unlike conventional rail-to-rail comparators that use both NMOS and PMOS input devices, the proposed design takes advantage of zero-V t NMOS devices that are available in many CMOS processes tailored for analog and mixed signal applications. Design issues associated with the use of zero-V t devices in comparator circuits are analyzed. Based on a 0.13 μm CMOS technology, the proposed design is compared with recently reported sub 1 V comparators and it shows significant performance improvement by the proposed design.