A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V
IEEE Transactions on Circuits and Systems II: Express Briefs
An improved low offset latch comparator for high-speed ADCs
Analog Integrated Circuits and Signal Processing
A 0.5 V high-speed comparator with rail-to-rail input range
Analog Integrated Circuits and Signal Processing
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This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.