Analyses of static and dynamic random offset voltages in dynamic comparators
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Fast, non-Monte-Carlo estimation of transient performance variation due to device mismatch
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A 0.5 V high-speed comparator with rail-to-rail input range
Analog Integrated Circuits and Signal Processing
A high-speed latched comparator with low offset voltage and low dissipation
Analog Integrated Circuits and Signal Processing
| Hi-index | 0.00 |
A comparator comprises a cross coupled circuit which produces a positive feedback. In conventional comparators, the mismatch between the cross coupled circuits determines the trade-off between the speed, offset and the power consumption of the comparator. A new low-offset low-power dynamic comparator for analog-to-digital converters is introduced. The comparator benefits from two stages and two operational phases to reduce the offset voltage caused by the mismatch effect inside the positive feedback circuit. Rigorous statistical analysis yields the input referred offset voltage and the delay of the comparator based on the circuit random parameters. The derivations are verified with exhaustive Monte-Carlo simulations at various corner cases of the process. A comparison between typical comparator and the proposed comparator in 180nm and 90nm has been made. The power consumption of the proposed comparator is about 44% of the conventional and its offset voltage is at least one-third of other mentioned conventional comparators.