Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture

• Authors: Vijay U.K.;Amrutur Bharadwaj
• Venue: VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
• Year: 2007

A novel comparator architecture is proposed for high speed operation in low voltage environment. Performance comparison with a conventional regenerative comparator shows a speed-up of 41%. The proposed comparator is embedded in a continuous time Sigma-delta ADC so as to reduce the quantizer delay and hence minimizes the excess loop delay problem. A performance enhancement of 1dB in the dynamic range of the ADC is achieved with this new comparator. We have implemented this ADC in a standard single-poly 8-Metal 0.13ìm UMC process. The entire system operates at 1.2V supply providing a dynamic range of 32dB consuming 720ìW of power and occupies an area of 0.1mm2