Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
Proceedings of the 2006 international symposium on Low power electronics and design
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents and evaluates three novel memory decoder designs which reduce energy consumption and delay by using selective precharging. These three designs, the AND-NOR, Sense-Amp, and the AND decoder, range in selectivity and select-line swing; these schemes charge and discharge fewer select-lines. This in turn consumes less energy than nonselective address decoders which charge and discharge all select-lines each cycle. These three decoding schemes are comprehensively simulated and compared to the conventional nonselective NOR decoder using 65nm CMOS technology. Energy, delay, and area calculations are provided for all four 4-to-16 decoders under analysis. The most selective AND decoder performs best and dissipates between 61% and 99% less (73% less on average) and the selective Sense-Amp decoder performs only slightly worse by dissipating between 58% and 75% less (66% less on average) energy than dissipated by the NOR decoder. The AND-NOR decoder dissipates between 15% less and 20% more (6% more on average) energy than dissipated by the NOR decoder. In addition, the AND decoder is 7.5% and the Sense-Amp decoder is 5.0% faster than the NOR decoder, however, the AND-NOR decoder is 1.7% slower than the NOR decoder.