Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Low-power CMOS with supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Six subthreshold full adder cells characterized in 90 nm CMOS technology
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Impact of supply voltage variations on full adder delay: analysis and comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS fulladder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.