A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Analysis of forward error correction methods for nanoscale networks-on-chip
Proceedings of the 2nd international conference on Nano-Networks
On hamming product codes with type-II hybrid ARQ for on-chip interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers
International Journal of Computer Applications in Technology
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This paper presents a methodology for designing System-On-Chip interconnection architectures providing a high level of protection from crosstalk and single-event upsets. An event driven simulator enriched with fault injection capabilities is exploited to evaluate the dependability level of the system being designed. The simulation environment supports several bus coding protocols and thus designers can easily evaluate different design alternatives. To enhance the dependability level of the interconnection architecture, we propose a distributed bus guardian scheme, where dedicated hardware modules monitor the integrity of the information transmitted over the bus and provide error correction mechanisms. Preliminary experimental results on a small benchmark system are reported showing the effectiveness of the proposed methodology.