A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
An efficient, fully adaptive deadlock recovery scheme: DISHA
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Performance Evaluation of Switch-Based Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Dynamic reconfiguration of node location in wormhole networks
Journal of Systems Architecture: the EUROMICRO Journal
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Packet Routing in Dynamically Changing Networks on Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
The modeling power of CINSim: Performance evaluation of interconnection networks
Computer Networks: The International Journal of Computer and Telecommunications Networking
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Advances in the technology of dynamic reconfigurable hardware allow enhanced architectures of interconnection networks for large scale down to on-chip parallel and distributed systems. To archive a higher communication performance the topology of the interconnection network can be reconfigured at runtime to support the particular communication profile of the active applications. One important issue concerning the reconfiguration of the network is the prevention of packet losses. Altering the network topology leads to a new routing situation for the remaining packets. Two approaches are possible: emptying all buffers of the network before reconfiguration, called static reconfiguration, or rerouting of remaining packets after reconfiguration, referred to as dynamic reconfiguration. For the latter approach, a reconfiguration-aware routing scheme is required, which is presented in this paper. In addition, the static and dynamic approaches are discussed and compared concerning complexity and performance. It is shown that the increased efficiency of the dynamic approach becomes negligible, if current available technology is regarded.