Design and validation of computer protocols
Design and validation of computer protocols
Model checking for programming languages using VeriSoft
Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An open graph visualization system and its applications to software engineering
Software—Practice & Experience - Special issue on discrete algorithm engineering
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
Characterizing Correctness Properties of Parallel Programs Using Fixpoints
Proceedings of the 7th Colloquium on Automata, Languages and Programming
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
An Algorithmic Approach to Design Exploration
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
Generating Tests from Counterexamples
Proceedings of the 26th International Conference on Software Engineering
Enforcing Concurrent Temporal Behaviors
Electronic Notes in Theoretical Computer Science (ENTCS)
Adaptive Verification using Forced Simulation
Electronic Notes in Theoretical Computer Science (ENTCS)
Model checking and testing combined
ICALP'03 Proceedings of the 30th international conference on Automata, languages and programming
Least-violating control strategy synthesis with safety rules
Proceedings of the 16th international conference on Hybrid systems: computation and control
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Temporal logic is often used as the specification formalism for the automatic verification of finite state systems. The automatic temporal verification of a system is a procedure that returns a yes/no answer, and in the latter case also provides a counterexample. In this paper we suggest a new application for temporal logic, as a way of assisting the debugging of a concurrent or a sequential program. We employ temporal logic over finite sequences as a constraint formalism that is used to control the way we step through the states of the debugged system. Using such temporal specification and various search strategies, we are able to traverse the executions of the system and obtain important intuitive information about its behaviors. We describe an implementation of these ideas as a debugging tool.