Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Processor Description Languages
Processor Description Languages
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Increasing complexity, shortening time to market, and tight requirements of embedded systems require design methodologies that increase designer productivity without sacrificing design quality. To design at higher abstraction level, today two approaches exist: High-Level Synthesis (HLS) and Application-Specific Instruction-Set Processors (ASIP). HLS mostly focuses on smaller applications and allows little control over the quality of automatically generated micro-architecture. On the other hand, ASIP can handle larger applications but has a high overhead for smaller applications. It also has a complex flow and requires instruction-set design expertise. Therefore, a unifying design methodology is needed that addresses the shortcomings of both methodologies and can support applications ranging from small to large within a single framework. No-Instruction-Set-Computer (NISC) Technology is developed to be such unifying methodology. To simplify the design process and enable more aggressive datapath optimizations, in NISC, the instruction abstraction is replaced with nanocodes that directly control the datapath components in every cycle. In my PhD, I focused on different challenges of synthesizing efficient NISC processors and generating hardware. The first part of my thesis focuses on developing an Architecture Description Language (ADL) that captures NISC processors for compilation and synthesis. This ADL is called Generic Netlist Representation (GNR) which is a strongly-typed, aspect-oriented ADL for describing netlist of NISC processors. The rest of my thesis focuses on some of the possible controller and datapath optimizations that affect performance, area, and power consumption of NISC processors. For instance, I present a hybrid approach that optimizes the binary code to reduce both the code size and the switching activity of the datapath. I also discuss how a given datapath can be customized and optimized for an application through an aggressive resource sharing. As part of this thesis, two tools have been developed: (1) an RTL generator tool that converts GNR to synthesizable Verilog code; and (2) a datapath refiner tool that customizes a given datapath for an application within a given performance constraint. Both tools are integrated into NISC toolset and are available online at http://www.cecs.uci.edu/∼nisc/.