Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Accelerating loops for coarse grained reconfigurable architectures using instruction extensions
Proceedings of the 2011 ACM Symposium on Research in Applied Computation
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In the automatic design of custom instruction set proces- sors, there can be a very large set of potential custom in- structions, from which a few instructions are required to be chosen, taking into account their spatial as well as temporal reuse and cost. Using the existing pattern matching tech- niques, finding complete reuse of every identified pattern in the entire application would be very slow and may even be computationally infeasible. Due to this, the existing selec- tion methods employ pattern matching techniques at a very later stage of selection process on a small set of patterns, compromising the quality of selected candidates. In this pa- per, we propose a method by which each pattern's reuse information can be derived at an early stage of selection process even when there are very large number of poten- tial patterns. The novel contributions of this paper include a simple and efficient algorithm for finding all the isomor- phic convex subgraphs (termed as Recurring Pattern Infor- mation(RPI)) of the given application's Control Data Flow Graph (CDFG). The proposed technique is integrated into the estimation phase of the Instruction Set Extension(ISE) automation. Experimental results show the efficiency of the proposed algorithm and demonstrate its utility in generating high quality custom instructions.