Owl: next generation system monitoring
Proceedings of the 2nd conference on Computing frontiers
Voronoi-diagram based heuristics for the location of mobile and unreliable service providers
ACST'06 Proceedings of the 2nd IASTED international conference on Advances in computer science and technology
Prototyping Multiprocessor System-on-Chip Applications: A Platform-Based Approach
IEEE Distributed Systems Online
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Thread warping: a framework for dynamic synthesis of thread accelerators
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Exposing non-standard architectures to embedded software using compile-time virtualisation
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Building heterogeneous reconfigurable systems with a hardware microkernel
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware supported task scheduling on dynamically reconfigurable SoC architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel thread scheduler design for polymorphic embedded systems
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
A run-time partitioning algorithm for RTOS on reconfigurable hardware
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
| Hi-index | 4.10 |
Components that combine a CPU and reconfigurable logic gates need a programming model that abstracts the computational hardware.