Hybrid Soft Error Detection by Means of Infrastructure IP Cores

Authors:
L. Bolzani;M. Rebaudengo;M. Sonza Reorda;F. Vargas;M. Violante
Affiliations:
Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Brazil;Politecnico di Torino, Italy;Politecnico di Torino, Italy;Politecnico di Torino, Italy;Politecnico di Torino, Italy
Venue:
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Year:
2004

Citing 0
Cited 2

Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems

Journal of Electronic Testing: Theory and Applications
A New Hybrid Fault Detection Technique for Systems-on-a-Chip

IEEE Transactions on Computers

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Abstract

In this paper, we propose a novel on-chip circuit to measurethe jitter present at the output of Phase-Locked-Loops(PLLs) used for synthesizing a clock with equal or higherfrequency than the input clock.This measure is performedat every period of the ...