Prediction in Dynamic SDRAM Controller Policies
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
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As the gap between processor speed and memory speed continues to increase, memory system becomes the bottleneck of the processor. Multiple instructions queuing for accessing main memory appear frequently, the regular changes of the access address stream often appear as well. Utilizing the characteristics of memory access, and considering different speeds of accessing DRAM in the hit, empty and conflict miss cases, this paper proposes a DRAM precharge policy based on address analysis. By collecting statistical information of address distribution of all the instructions waiting for accessing memory, and analyzing the regular changes of access addresses, this method can predict the access of each bank, make judgment of the appropriate moment to precharge each DRAM bank. The experimental results show that comparing with the commonly used close page and open page precharge policies, this method can decrease the cycles per instruction by 15.7% and 4.3% respectively.