A comparison of dynamic branch predictors that use two levels of branch history
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Proceedings of the 27th annual international symposium on Computer architecture
Design Issues and Tradeoffs for Write Buffers
HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
MisSPECulation: partial and misleading use of SPEC CPU2000 in computer architecture conferences
Proceedings of the 30th annual international symposium on Computer architecture
The Definitive BIOS Optimization Guide
The Definitive BIOS Optimization Guide
Adaptive History-Based Memory Schedulers
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
A DRAM Precharge Policy Based on Address Analysis
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Rank idle time prediction driven last-level cache writeback
Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
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Memory access latency can limit microcontroller system performance. SDRAM access control policies impact latency through SDRAM device state. It is shown that execution time can be reduced by using a state machine which predicts, for each access, the policy which will minimize latency. Two-level dynamic predictors are incorporated into the SDRAM controller. A range of organizations for dynamic predictors are described, and the performance improvements predicted by simulation are compared using execution time and prediction accuracy as metrics. Results show that predictive SDRAM controllers, reduce execution time by 1.6% to 17% over static access control policies. The prediction accuracy of the best predictor results in 93% prediction accuracy, with 87% accuracy for OP state preferred accesses, and 96% for CPA state preferred accesses. Results show that execution time is strongly correlated to the prediction accuracy of OP, suggesting directions for future predictor development.