FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
R70-40 Module Clustering to Minimize Delay in Digital Networks
IEEE Transactions on Computers
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Survey of computer-aided electrical analysis of integrated circuit interconnections
IBM Journal of Research and Development
Efficient algorithm for the partitioning of trees
IBM Journal of Research and Development
Implementing and clustering modules with complex delays
Integration, the VLSI Journal
Synthesis algorithm for application-specific homogeneous processor networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Netlist bipartitioning using particle swarm optimisation technique
International Journal of Artificial Intelligence and Soft Computing
| Hi-index | 14.98 |
An important aspect of the packaging of digital networks is the allocation of logic gates to modules such that a predetermined objective function is minimized. In order to develop techniques for this partitioning of a logic network we have considered the following problem: Given an acyclic combinational network composed of various primitive blocks such as NOR gates, assume that a maximum of M gates can be "clustered" together into larger modules, and that a maximum of P pins can be accommodated in each larger module. Assume also that in a network composed of such larger modules, no delay is encountered on the interconnections linking two gates internal to a module and a delay of one time unit is encountered on interconnections linking two gates in different modules . Find an easily applied algorithm that will result in a network such that the maximum delay through the network is minimized.