Finding Maximum on an Array Processor with a Global Bus

Authors:
S. H. Bokhari
Affiliations:
Department of Electrical Engineering, University of Engineering and Technology
Venue:
IEEE Transactions on Computers
Year:
1984

Citing 4
Cited 6

On an improved algorithm for decentralized extrema finding in circular configurations of processors

Communications of the ACM
Decentralized extrema-finding in circular configurations of processors

Communications of the ACM
Ethernet: distributed packet switching for local computer networks

Communications of the ACM
Lookahead networks

AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference

Assignment of job modules onto array processors

IEEE Transactions on Computers
Timing for Associative Operations on the MASC Model

IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Optimal Bounds for Finding Maximum on Array of Processors with k Global Buses

IEEE Transactions on Computers
The organization of permutation architectures with bussed interconnections

SFCS '87 Proceedings of the 28th Annual Symposium on Foundations of Computer Science
Linear array with a reconfigurable pipelined bus system - Concepts and applications

Information Sciences: an International Journal
Parallel recognition and parsing on mesh connected computers with multiple broadcasting

Computer Languages

Quantified Score

Hi-index	14.99

Visualization

Abstract

The problem of finding the maximum of a set of values stored one per processor on an n X n array of processors is analyzed. The array has a time-shared global bus in addition to conventional processor-processor links. A two-phase algorithm for finding the maximum is presented that uses conventional links during the first phase and the global bus during the second. This algorithm is faster than algorithms that use either only the global bus or only the conventional links.