The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Computational Aspects of VLSI
Finding Maximum on an Array Processor with a Global Bus
IEEE Transactions on Computers
Optimal Bounds for Finding Maximum on Array of Processors with k Global Buses
IEEE Transactions on Computers
SFCS '86 Proceedings of the 27th Annual Symposium on Foundations of Computer Science
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This paper explores the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations. By connecting chips with shared bus interconnections, as opposed to point-to-point interconnections, we show that the number of pins per chip can often be reduced. For example, for infinitely many n, we exhibit permutation architectures with ⌈√n⌉ pins per chip that can realize any of the n cyclic shifts on n chips in one clock tick. When the set of permutations forms a group with p elements, any permutation in the group can be realized in one clock tick by an architecture with O(√p lg p) pins per chip. When the permutation group is abelian, O(√p) pins suffice. These results are all derived from a mathematical characterization of uniform permutation architectures based on the combinatorial notion of a difference cover.