Hazard Correction in Synchronous Sequential Circuits

  • Authors:

  • M. Servit

  • Affiliations:

  • Department of Computers, Electrotechnical Faculty, Czech Polytechnical Institute

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1975

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Abstract

Limitations which are placed on input and clock signals of single and double-rank synchronous sequential circuits with memory composed of level-triggered flip-flops are presented and compared with the results of Unger [1] and Curtis [2].