Hazard Correction in Synchronous Sequential Circuits
IEEE Transactions on Computers
A New Double-Rank Realization of Sequential Machines
IEEE Transactions on Computers
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A new type of double-rank synchronous sequential machine is introduced in this paper. Its dissimilarities and similarities with the other types (Types 1 and 2) of double-rank sequential machines are discussed along with the relative merits of each type. Providing a striking example of the advantages of this new type (called Type 3) double-rank machine is a new kind of binary counter, which is highly reliable, fast, and efficient. Circuit realizations of Type 3 double-rank sequential machines can be derived by using a slight variation of a method presently used for Type 2 double-rank machines. This paper shows how the method can be markedly improved.