Introduction to VLSI Systems
An Implementation of Mixed-Radix Conversion for Residue Number Applications
IEEE Transactions on Computers
A new Mixed Radix Conversion algorithm MRC-II
Journal of Systems Architecture: the EUROMICRO Journal
Optimum RNS sign detection algorithm using MRC-II with special moduli set
Journal of Systems Architecture: the EUROMICRO Journal
Design Methods of Radix Converters Using Arithmetic Decompositions
IEICE - Transactions on Information and Systems
Efficient Multiplication of Polynomials on Graphics Hardware
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
Cox-Rower architecture for fast parallel montgomery multiplication
EUROCRYPT'00 Proceedings of the 19th international conference on Theory and application of cryptographic techniques
Hi-index | 14.98 |
A new, fully parallel mixed-radix conversion (MRC) algorithm which utilizes the maximum parallelism that exists in the residues (RNS) to mixed-radix (MR) digits conversion to achieve high throughput rate and very short conversion time is presented. The new algorithm has a conversion time of two table look-up cycles for moduli sets consisting of up to 15 moduli. As a comparison, the classical Szabo and Tanaka MRC algorithm has a conversion time of (n - 1) clock cycles for an n-moduli RNS. This algorithm can be implemented by off-the-shelf ECL IC's to achieve a conversion time of 50 ns and a throughput rate of 40 MHz for a 150-bit RNS.