Online pipeline systems for recursive numeric computations
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
On-line algorithms for the design of pipeline architectures
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
A pipelined processing unit for on-line division
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
An On-Line Square Root Algorithm
IEEE Transactions on Computers
An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines
IEEE Transactions on Computers
On-Line Algorithms for Division and Multiplication
IEEE Transactions on Computers
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Research in computer architecture in the last decade has been driven largely by the motivation to overcome the "von Neumann" bottleneck. This paper describes the design and use of one such architecture fully digit on-line networks. First, digit on-line algorithms and processing are defined. The key advantage to digit on-line processing is that it allows a digit serial, most significant digit first, type of data flow. Processing of the most significant operand digits starts immediately and generation of the most significant result digits soon follows. The minimum set of primitive logic operations required to implement a digit on-line processing component in VLSI are outlined. Then, digit on-line networks consisting of many of these digit on-line components are examined. Finally, two different network configurations are discussed and compared.