The Parallel Evaluation of Arithmetic Expressions Without Division
IEEE Transactions on Computers
The delay of circuits whose inputs have specified arrival times
Discrete Applied Mathematics
Reduction of Depth of Boolean Networks with a Fan-In Constraint
IEEE Transactions on Computers
Hi-index | 14.98 |
A Boolean expression wilth n literals, i.e., n distinct appearances of variables, can be evaluated by a parallel processing system in at most 1.81 log2n steps, or, equivalently, by a network constructed with two-input AND and OR gates and having at most 1.81 log2n levels.