Reduction of Depth of Boolean Networks with a Fan-In Constraint

  • Authors:

  • F. P. Preparata;D. E. Mulller;A. B. Barak

  • Affiliations:

  • Coordinated Science Laboratory and Department of Electrical Engineering, University of Illinois;-;-

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1977

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Abstract

In this paper we presentt family of techniques for the design of combinational networks whose objective is the reduction of the number of levels, subject to a constraint on the fan-in of the logic gates. We show that a Boolean expression with n literals and involving the connectivest AND and OR can be restructured so that the resulting network of AND and OR gates has depth at most Cllog