On the Time Required to Perform Addition
Journal of the ACM (JACM)
On the Time Required to Perform Multiplication
Journal of the ACM (JACM)
Speedup of iterative programs in multiprocessing systems.
Speedup of iterative programs in multiprocessing systems.
IEEE Transactions on Computers
The Parallel Evaluation of Arithmetic Expressions Without Division
IEEE Transactions on Computers
Reduction of Depth of Boolean Networks with a Fan-In Constraint
IEEE Transactions on Computers
An Algorithm for High-Speed Digital Filters
IEEE Transactions on Computers
Time and Parallel Processor Bounds for Linear Recurrence Systems
IEEE Transactions on Computers
On the Addition of Binary Numbers
IEEE Transactions on Computers
IEEE Transactions on Computers
| Hi-index | 15.00 |
New results are given concerning the design of combinational logic circuits. We give time and component bounds for combinational circuits specified in several ways. For any sequential machine defined by linear recurrence relations, we discuss an algorithm for the synthesis of equivalent combinational logic. The procedure includes upper bounds on the time and components involved. We also discuss the transformation of nonlinear recurrences into combinational circuits. Examples are given using gates as well as IC's as components. These include binary addition, multiplication, and ones' position counting. The time and component bounds our procedure yields compare favorably with traditional results.