Logic Design of Digital Systems
Logic Design of Digital Systems
DAC '68 Proceedings of the 5th annual Design Automation Workshop
An Algorithm for Synthesis of Multiple-Output Combinational Logic
IEEE Transactions on Computers
Reduced Solutions of Boolean Equations
IEEE Transactions on Computers
A computer program for the synthesis of combinational switching circuits
FOCS '61 Proceedings of the 2nd Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1961)
Simplifying Circuits for Formal Verification Using Parametric Representation
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
An Approach to Unified Methodology of Combinational Switching Circuits
IEEE Transactions on Computers
Comments on ``Equational Logic''
IEEE Transactions on Computers
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A method has been investigated for the synthesis of memoryless logical networks using a restricted repertoire of functional modules. The method is based on the reduced general solution to a generalized system of Boolean equations (BE) as applied to the decomposition of Boolean functions. The aim of the synthesis is to obtain the most constrained circuit having at most two levels of gating. The constraints take the form of single input variables or constant logic levels applied to the inputs of the first level gate. This is achieved by assembling a set of constraint equations which are then a part of the generalized system of BE. The method is then tested on some synthesis examples of single and multiple output functions in terms of the NAND and (WOS) modules.