Uniform modular realization of sequential machines
ACM '68 Proceedings of the 1968 23rd ACM national conference
Universal Modular Trees: A Design Procedure
IEEE Transactions on Computers
Uniform Decomposition of Incompletely Specified Sequential Machines
IEEE Transactions on Computers
R70-29 Uniform Synthesis of Sequential Circuits
IEEE Transactions on Computers
Minimum Universal Logic Module Sequential Circuits with Decoders
IEEE Transactions on Computers
Synchronous Sequential Machines: A Modular and Testable Design
IEEE Transactions on Computers
IEEE Transactions on Computers
An application of cellular logic for high speed decoding of minimum-redundancy codes
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
Iteratively Realized Sequential Circuits
IEEE Transactions on Computers
State assignment for realizing modular input-free sequential logical networks without invertors
Journal of Computer and System Sciences
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Abstract A "synthesis technique" is presented for "realizing" any arbitrary binary input-binary output "synchronous sequential Moore machine" in the form of a network composed of identical 2-state "component machines." With slight modification the synthesis technique presented can be used to realize any given n-input-p-output synchronous sequential Moore machine in the form of a network composed of identical 2-state component machines.