The Architectural Elements of a Symmetric Fault-Tolerant Multiprocessor
IEEE Transactions on Computers
SIFT: software implemented fault tolerance
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
Design of a fault-tolerant, modular computer with dynamic redundancy
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
An overview of fault-tolerant digital system architecture
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Pluribus: a reliable multiprocessor
AFIPS '75 Proceedings of the May 19-22, 1975, national computer conference and exposition
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A distributed fault-tolerant information processing system is proposed, comprising a central multiprocessor, dedicated local processors, and multiplexed input-output buses connecting them together. The processors in the multiprocessor are duplicated for error detection, which is felt to be less expensive than using coded redundancy of comparable effectiveness. Error recovery is made possible by a triplicated scratchpad memory in each processor. The main multiprocessor memory uses replicated memory for error detection and correction. Local processors use any of three conventional redundancy techniques: voting, duplex pairs with backup, and duplex pairs in independent subsystems.