The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Data flow languages and architectures
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Two Fundamental Limits on Dataflow Multiprocessing
Two Fundamental Limits on Dataflow Multiprocessing
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP
ACM Transactions on Architecture and Code Optimization (TACO)
Concepts, Techniques, and Models of Computer Programming
Concepts, Techniques, and Models of Computer Programming
ACM SIGPLAN Notices
Area-Performance Trade-offs in Tiled Dataflow Architectures
Proceedings of the 33rd annual international symposium on Computer Architecture
Computer
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Dataflow architectures showed considerable potential however the initial interest has to some extent petered out. Difficulties arose with the cost of implementation, appropriate programming languages and operating systems, and ability to sustain development. We argue that there is a fundamental problem with dataflow relating to how a program is represented. This article explores representing a program by an unlimited acyclic network rather than a fixed one with either cycles or reuse. The state is captured in the edges rather than the nodes. We show how this model can address many of the shortcomings of dataflow and enable dataflow to realize its expected potential. The model shows promise in: improving parallelism and ease of implementation.