A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform

Authors:
Huan-Kai Peng;Chun-Hsin Lee;Jian-Wen Chen;Tzu-Jen Lo;Yung-Hung Chang;Sheng-Tsung Hsu;Yuan-Chun Lin;Ping Chao;Wei-Cheng Hung;Kai-Yuan Jan
Affiliations:
Department of Computer Science, National Tsing Hua University, Taiwan;Department of Computer Science, National Tsing Hua University, Taiwan;Department of Computer Science, National Tsing Hua University, Taiwan;Department of Computer Science, National Tsing Hua University, Taiwan;Department of Computer Science, National Tsing Hua University, Taiwan;Department of Computer Science, National Tsing Hua University, Taiwan;Department of Computer Science, National Tsing Hua University, Taiwan;Department of Computer Science, National Tsing Hua University, Taiwan;Department of Computer Science, National Tsing Hua University, Taiwan;Department of Computer Science, National Tsing Hua University, Taiwan
Venue:
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Year:
2007

Citing 0
Cited 3

VisoMT: a collaborative multithreading multicore processor for multimedia applications with a fast data switching mechanism

IEEE Transactions on Circuits and Systems for Video Technology
An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration

ACM Transactions on Embedded Computing Systems (TECS)
Practical design space exploration of an h264 decoder for handheld devices using a virtual platform

PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present a hardwired decoder prototype for H.264/AVC main profile video. Our design takes as its input compressed H.264/AVC bit-stream and produces as its output video frames ready for display. We wrap the decoder core with an AMBA-AHB bus interface and integrate it into a multimedia SoC platform. Several architectural innovations at both IP and system levels are proposed to achieve very high performance at very low operating frequency. Running at 16MHz, our FPGA demo system is able to real-time decode CIF (352脳288) video at 30 frames per second. Moreover, we take system cost into consideration such that only a single external SDRAM is needed and memory traffic minimized.