Proceedings of the 2004 conference on Applications, technologies, architectures, and protocols for computer communications
Part II: control theory for buffer sizing
ACM SIGCOMM Computer Communication Review
Scalable network virtualization using FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
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Recent theoretical results in buffer sizing research suggest that core Internet routers can achieve high link utilization, if they are capable of storing only a handful of packets. The underlying assumption is that the traffic is non-bursty, and that the system is operated below 85-90% utilization. In this paper, we present a test-bed for buffer sizing experiments using NetFPGA [2], a PCI-form factor board that contains reprogrammable FPGA elements, and four Gigabit Ethernet interfaces. We have designed and implemented a NetFPGA-based Ethernet switch with finely tunable buffer sizes, and an event capturing system to monitor buffer occupancies inside the switch. We show that reducing buffer sizes down to 20-50 packets does not necessarily degrade system performance.