IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With extensive use of Dynamic Voltage Scaling (DVS) there is increasing need for voltage scalable models. Simi- larly, leakage being very sensitive to temperature motivates the need for a temperature scalable model as well. We characterize standard cell libraries for statistical leakage analysis based on models for transistor stacks. Modeling stacks has the advantage of using a single model across many gates there by reducing the number of models that need to be characterized. Our experiments on 15 differ- ent gates show that we needed only 23 models to predict the leakage across 126 input vector combinations. We in- vestigate the use of neural networks for the combined PVT model, for the stacks, which can capture the effect of in- ter die, intra gate variations, supply voltage(0.6-1.2V) and temperature(0-1000C) on leakage. Results show that neu- ral network based stack models can predict the PDF of leak- age current across supply voltage and temperature accu- rately with the average error in mean being less than 2% and that in standard deviation being less than 5% across a range of voltage, temperature.