Modeling, verification, and implementation of PLC program using timed-MPSG

  • Authors:

  • Devinder Thapa;S. C. Park;C. M. Park;Gi-Nam Wang

  • Affiliations:

  • AJOU University, Suwon, South Korea;AJOU University, Suwon, South Korea;AJOU University, Suwon, South Korea;AJOU University, Suwon, South Korea

  • Venue:
  • Proceedings of the 2007 Summer Computer Simulation Conference
  • Year:
  • 2007

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Abstract

In this paper, we proposed a methodology to model, verify, and generate IEC standard PLC code using Timed-MPSG (an extended version of finite state automata). It can reduce PLC development time and the errors that generally occur when PLC programs are manually programmed. For this purpose, we used Timed-MPSG to model the formal specification of the targeted shop floor controller system, after that, the graphical representation of Timed-MPSG is converted to the textual format automatically. Thereafter, the textural structure of Timed-MPSG translated into input code for model checker (SMV) - for the purpose of formal verification. Although, the simulation can be used to verify the written code, however, the use of formal methods for verification is more desirable to validate the state model for hidden errors. After verifying the model against specified properties, written in temporal logic, finally, generation of programmable logic controller code by using one-to-one mapping technique. The similarity in the hierarchical and modular architecture of Timed-MPSG, SMV and IEC standard PLC program, made it convenient to transform from one form to another as described in our proposed method. Furthermore, an illustration of methodology to PLC design and development is explained with a suitable example.