Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Soft Errors in Advanced Computer Systems
IEEE Design & Test
Multiple Transient Faults in Logic: An Issue for Next Generation ICs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Online hardening of programs against SEUs and SETs
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies
ETS '07 Proceedings of the 12th IEEE European Test Symposium
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
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A single radiation induced transient can cause multiple errors in a circuit. Hardware and time-based mitigation solutions able to handle multiple errors can be very expensive in terms of area and performance. To face this problem, recomputation has been proposed as a means to cope with transient errors in this new scenario. In this paper, we discuss the effects of the levels of granularity in the recomputation process, and the verification time cost, in the final application execution time when dealing with multiple errors.