An enhanced canary-based system with BIST for SRAM standby power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System
Journal of Signal Processing Systems
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We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SRAM module is reduced from 550mV to 220mV. A novel error-tolerant architecture further reduces the minimum static-error-free VDD to 155mV. With a 100mV noise margin, a 255mV standby VDD effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1V VDD.