Amortized efficiency of list update and paging rules
Communications of the ACM
Wide area traffic: the failure of Poisson modeling
IEEE/ACM Transactions on Networking (TON)
Explicit allocation of best-effort packet delivery service
IEEE/ACM Transactions on Networking (TON)
Online computation and competitive analysis
Online computation and competitive analysis
Competitve buffer management for shared-memory switches
Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures
Dynamic routing on networks with fixed-size buffers
SODA '03 Proceedings of the fourteenth annual ACM-SIAM symposium on Discrete algorithms
Buffer Overflow Management in QoS Switches
SIAM Journal on Computing
Packet-mode policies for input-queued switches
Proceedings of the sixteenth annual ACM symposium on Parallelism in algorithms and architectures
Harmonic buffer management policy for shared memory switches
Theoretical Computer Science - Special issue: Online algorithms in memoriam, Steve Seiden
On the Performance of Greedy Algorithms in Packet Buffering
SIAM Journal on Computing
Packet-mode emulation of output-queued switches
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
Scheduling policies for CIOQ switches
Journal of Algorithms
An improved algorithm for CIOQ switches
ACM Transactions on Algorithms (TALG)
Maximizing throughput in multi-queue switches
Algorithmica
An experimental study of new and known online packet buffering algorithms
ESA'07 Proceedings of the 15th annual European conference on Algorithms
Matching output queueing with a combined input/output-queued switch
IEEE Journal on Selected Areas in Communications
Output-queued switch emulation by fabrics with limited memory
IEEE Journal on Selected Areas in Communications
Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures
A survey of buffer management policies for packet switches
ACM SIGACT News
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The buffered crossbar switch architecture has recently gained considerable research attention. In such a switch, besides normal input and output queues, a small buffer is associated with each crosspoint. Due to the introduction of crossbar buffers, output and input contention is eliminated, and the scheduling process is greatly simplified. We analyze the performance of switch policies by means of competitive analysis, where a uniform guarantee is provided for all traffic patterns. We assume that each packet has an intrinsic value designating its priority and the goal of the switch policy is to maximize the weighted throughput of the switch. We consider FIFO queueing buffering policies, which are deployed by the majority of today's Internet routers. In packet-mode scheduling, a packet is divided into a number of unit length cells and the scheduling policy is constrained to schedule all the cells contiguously, which removes reassembly overhead and improves Quality-of-Service (QoS). For the case of variable length packets with uniform value density (Best Effort model), where the packet value is proportional to its size, we present a packet-mode greedy switch policy that is 7-competitive. For the case of unit size packets with variable values (Differentiated Services model), we propose a preemptive greedy switch policy that achieves a competitive ratio of 21. As far as we know, this is the first constant-competitive FIFO policy for this architecture in the case of variable value packets. The presented policies are simple and thus can be efficiently implemented at high speeds. Moreover, our results hold for any value of the internal switch fabric speedup.