Technologies for low latency interconnection switches

Authors:
Thomas F. Knight, Jr.
Affiliations:
M.I.T. Artificial Intelligence Laboratory
Venue:
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
Year:
1991

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Abstract

This paper presents an engineering design for a low latency high bandwidth interconnection network which will form the switching substrate for a multi-model parallel processing system. The performance is enhanced with a variety of approaches covering interconnection protocols, routing, fault tolerance, advanced packaging, and electrical interconnection techniques. The synergistic application of these technologies leads to a high performance design.