Shared cache multiprocessing with pack computers
ACM SIGARCH Computer Architecture News
Some innovations in computer architecture
ACM SIGARCH Computer Architecture News
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A compiler controlled pack cache allows the compiler to plan the allocation of the cache memory to minimize thrashing, group memory accesses, and specify strided transfers between the cache and main memory, thereby achieving a higher usable bandwidth and reducing the overall miss delay.Since it will soon be reasonable to have on-chip DRAM memories of 4 Mbits (512k bytes), a size comparable to the personal computer main memories of several years ago, the accesses to main memory will become more like the disc input/output of personal computers of several years ago.Message passing between adjacent devices will likely supplant busses, e.g. processor to DRAM to DRAM to DRAM to SCSI controller to keyboard controller, etc. Message passing is inherently faster than a buss.