Contention is no obstacle to shared-memory multiprocessing
Communications of the ACM - Special issue on parallelism
Vector access performance in parallel memories using skewed storage scheme
IEEE Transactions on Computers
Classification Categories and Historical Development of Circuit Switching Topologies
ACM Computing Surveys (CSUR)
Computer Structures: Principles and Examples
Computer Structures: Principles and Examples
Hector: A Hierarchically Structured Shared-Memory Multiprocessor
Computer - Special issue on experimental research in computer architecture
Algorithms for scalable synchronization on shared-memory multiprocessors
ACM Transactions on Computer Systems (TOCS)
Process coordination with fetch-and-increment
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Synchronization without contention
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The compiler controlled pack cache and messaging
ACM SIGARCH Computer Architecture News
A conflict-free memory design for multiprocessors
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Methods for message routing in parallel machines
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Operating system support for parallel programming on RP3
IBM Journal of Research and Development
Fast Algorithms for Routing Around Faults in Multibutterflies and Randomly-Wired Splitter Networks
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Performance Evaluation of Switch-Based Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
A lightweight idempotent messaging protocol for faulty networks
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
A Parallel Algorithm for Reconfiguring a Multibutterfly Network with Faulty Switches
IEEE Transactions on Computers
Redsharc: a programming model and on-chip network for multi-core systems on a programmable chip
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Hi-index | 4.10 |
The Monarch architecture team took advantage of custom VLSI in the design of a shared-memory parallel processor. The simple structure eases the task of programming a massively parallel machine.