Hierarchical cache/bus architecture for shared memory multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Distributing Hot-Spot Addressing in Large-Scale Multiprocessors
IEEE Transactions on Computers
Design Tradeoffs for Process Scheduling in Shared Memory Multiprocessor Systems
IEEE Transactions on Software Engineering
Computer
Portable Programs for Parallel Processors
Portable Programs for Parallel Processors
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Recently there has been considerable interest in cache coherency protocols in shared-memory multiprocessor systems, particularly in protocols which are scalable, i.e. efficient in very large systems. In this position paper, it will be argued that in most multiprocessor applications scalability---or for that matter, systemwide cache coherency itself---is unnecessary, no matter how large the system is. Since even an efficient protocol will be a significant inhibitor of performance, it is then argued that systems not be built with systemwide coherency. Instead, a concept of "local coherency" is proposed. In this approach, though the shared-memory paradigm is retained and the system is still assumed to consist of a very large number of processors, hardware support for accessing shared variables exists only within groups of processors. Accordingly, it is asserted that the main research in cache coherency protocols should concentrate on developing efficient protocols for small and medium numbers of caches rather than on scalability.