Digital signal processing (3rd ed.): principles, algorithms, and applications
Digital signal processing (3rd ed.): principles, algorithms, and applications
VHDL Core for 1024-Point Radix-4 FFT Computation
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
Coarse frequency estimation using the discrete Fourier transform (Corresp.)
IEEE Transactions on Information Theory
IEEE Transactions on Consumer Electronics
A canonic-signed-digit coded genetic algorithm for designing finite impulse response digital filter
Digital Signal Processing
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This paper presents a novel algorithm, called the DFSWT, and its FPGA-based hardware processing unit for frequency estimation of a time series main periodic component. Since the DFSWT uses just additions and subtractions, it is simpler to compute than the FFT, and since its spectrum is a frequency function, it is more intuitive than the Walsh transform. The results show that the proposed algorithm is very efficient in detecting the frequency of the main periodic component, even in low SNR. The proposed hardware processing unit is 3 orders of magnitude faster than its respective software implementation and presents advantages regarding to power consumption, footprint, and computation speed against highly optimized commercially available FFT cores.