Software pipelining for transport-triggered architectures

Authors:
Jan Hoogerbrugge;Henk Corporaal;Hans Mulder
Affiliations:
Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital Systems;Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital Systems;Delft University of Technology, Department of Electrical Engineering, Section Computer Architecture and Digital Systems
Venue:
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Year:
1991

Optimal loop parallelization

PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-Offs

Computer
A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture

Selected papers of the second workshop on Languages and compilers for parallel computing
MOVE: a framework for high-performance processor design

Proceedings of the 1991 ACM/IEEE conference on Supercomputing
A Systolic Array Optimizing Compiler

A Systolic Array Optimizing Compiler
Interpreting machines: Architecture and programming of the B1700/B1800 series (Operating and programming systems series)

Interpreting machines: Architecture and programming of the B1700/B1800 series (Operating and programming systems series)

A dynamic-programming technique for compacting loops

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
A distributed, simultaneously multi-threaded (SMT) processor with clustered scheduling windows for scalable DSP performance

Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP

Hi-index	0.00