An FPGA Run-Time Parameterisable Log-Normal Random Number Generator

Authors:
Pedro Echeverría;David B. Thomas;Marisa López-Vallejo;Wayne Luk
Affiliations:
Dept. de Ingeniería Electrónica, Universidad Politécnica de Madrid, (Spain);Dept. of Computing, Imperial College London, (United Kingdom);Dept. de Ingeniería Electrónica, Universidad Politécnica de Madrid, (Spain);Dept. of Computing, Imperial College London, (United Kingdom)
Venue:
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2008

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Abstract

Monte Carlo financial simulation relies on the generation of random variables with different probability distribution functions. These simulations, particularly the random number generator (RNG) cores, are computationally intensive and are ideal candidates for hardware acceleration. In this work we present an FPGA based Log-normal RNG ideally suited for financial Monte Carlo simulations, as it is run-time parameterisable and compatible with variance reduction techniques. Our architecture achieves a throughput of one sample per cycle with a 227.6 MHz clock on a Xilinx Virtex-4 FPGA.