Using partial orders for the efficient verification of deadlock freedom and safety properties
Formal Methods in System Design - Special issue on computer-aided verification: special methods II
Symbolic model checking with rich assertional languages
Theoretical Computer Science
Regular Model Checking Made Simple and Efficient
CONCUR '02 Proceedings of the 13th International Conference on Concurrency Theory
Partial-Order Reduction in Symbolic State Space Exploration
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Extrapolating Tree Transformations
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
General decidability theorems for infinite-state systems
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Parameterized verification of infinite-state processes with global conditions
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Approximated Context-Sensitive Analysis for Parameterized Verification
FMOODS '09/FORTE '09 Proceedings of the Joint 11th IFIP WG 6.1 International Conference FMOODS '09 and 29th IFIP WG 6.1 International Conference FORTE '09 on Formal Techniques for Distributed Systems
Automatic Verification of Directory-Based Consistency Protocols
RP '09 Proceedings of the 3rd International Workshop on Reachability Problems
Equational abstraction refinement for certified tree regular model checking
ICFEM'12 Proceedings of the 14th international conference on Formal Engineering Methods: formal methods and software engineering
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Several recent works have considered parameterized verification, i.e. automatic verification of systems consisting of an arbitrary number of finite-state processes organized in a linear array. The aim of this paper is to extend these works by giving a simple and efficient method to prove safety properties for systems with tree-likearchitectures. A process in the system is a finite-state automaton and a transition is performed jointly by a process and its parent and children processes. The method derives an over-approximation of the induced transition system, which allows the use of finite trees as symbolic representations of infinite sets of configurations. Compared to traditional methods for parameterized verification of systems with tree topologies, our method does not require the manipulation of tree transducers, hence its simplicity and efficiency. We have implemented a prototype which works well on several nontrivial tree-based protocols.