LFP '88 Proceedings of the 1988 ACM conference on LISP and functional programming
Semantics with applications: a formal introduction
Semantics with applications: a formal introduction
NORMA: a graph reduction processor
LFP '86 Proceedings of the 1986 ACM conference on LISP and functional programming
A LISP garbage-collector for virtual-memory computer systems
Communications of the ACM
Research Directions in Parallel Functional Programming
Research Directions in Parallel Functional Programming
BWM: A Concrete Machine for Graph Reduction
Proceedings of the 1991 Glasgow Workshop on Functional Programming
Super-combinators a new implementation method for applicative languages
LFP '82 Proceedings of the 1982 ACM symposium on LISP and functional programming
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
The Implementation of Functional Programming Languages (Prentice-Hall International Series in Computer Science)
PADL'07 Proceedings of the 9th international conference on Practical Aspects of Declarative Languages
Proceedings of the 15th ACM SIGPLAN international conference on Functional programming
Introducing the PilGRIM: a processor for executing lazy functional languages
IFL'10 Proceedings of the 22nd international conference on Implementation and application of functional languages
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For the memory intensive task of graph reduction, modern PCs are limited not by processor speed, but by the rate that data can travel between processor and memory. This limitation is known as the von Neumann bottleneck. We explore the effect of wideningthis bottleneck using a special-purpose graph reduction machine with wide, parallel memories. Our prototype machine --- the Reduceron --- is implemented using an FPGA, and is based on a simpletemplate-instantiation evaluator. Running at only 91.5MHz on an FPGA, the Reduceron is faster than mature bytecode implementations of Haskell running on a 2.8GHz PC.