Proposal for LDPC Code Design System Using Multi-Objective Optimization and FPGA-Based Emulation

  • Authors:

  • Yukari Ishida;Hirotaka Nosato;Eiichi Takahashi;Masahiro Murakawa;Isamu Kajitani;Tatsumi Furuya;Tetsuya Higuchi

  • Affiliations:

  • Toho University, Chiba, Japan 274-8510;Toho University, Chiba, Japan 274-8510;National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan 305-8568;National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan 305-8568;National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan 305-8568;Toho University, Chiba, Japan 274-8510;National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan 305-8568

  • Venue:
  • ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
  • Year:
  • 2008

Quantified Score

Hi-index 0.00

Visualization

Abstract

The paper proposes a low density parity check (LDPC) code design system to facilitate the design of communication systems using LDPC codes for error correction. The proposed LDPC code design system has three advantages (utilization of MOGA to search codes, speed enhancement achieved through parallelization and FPGAs, and employment of more precise simulation models) and solves problems encountered when LDPC codes are used in practical applications. Preliminary evaluation results for the proposed system are presented, which demonstrate that the system can function successfully.