On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Model checking
Automata on Infinite Objects and Church's Problem
Automata on Infinite Objects and Church's Problem
FOCS '05 Proceedings of the 46th Annual IEEE Symposium on Foundations of Computer Science
Synthesis from scenario-based specifications
Journal of Computer and System Sciences
IJCAI'13 Proceedings of the Twenty-Third international joint conference on Artificial Intelligence
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One of the most significant developments in the area of design verification over the last decade is the development of of algorithmic methods for verifying temporal specification of finite-state designs [2]. A frequent criticism against this approach, however, is that verification is done after significant resources have already been invested in the development of the design. Since designs invariably contains errors, verification simply becomes part of the debugging process. The critics argue that the desired goal ought to be the use of the specification in the design development process in order to guarantee the development of correct designs. This is called design synthesis [1,4]. In this talk I will review 50 years of research on the synthesis problem and show how the automata-theoretic approach can be used to solve it [3,4,5].